Patent Document 1 describes a multi-port memory device that includes a plurality of ports for supporting external devices and serial input/output interfaces; and a plurality of banks for transmitting/receiving data in parallel with the ports. In the multi-port memory device, a plurality of global data buses support transmission/reception of data between the ports and the banks. In the multi-port memory device, during a test mode for testing a core area of the banks, a test input/output controller transmits, to the banks via the global data buses without passing through the ports, a test signal and a test input signal that are input from a plurality of pads to the ports. In response to the test signal, the test input/output controller transmits, to the pads via the global data buses, a test output signal output from the banks.
Further, Patent Document 2 describes a register file device including a data storage unit including a multi-port latch; and a writing unit that generates, from a clock signal and a plurality of sets of write control signals, write addresses, and write data, a write signal to be written to the data storage unit. The writing unit includes an address matching detecting circuit and a changing circuit. The address matching detecting circuit detects that at least two addresses of the plurality of write addresses match, and outputs an address matching signal for the matched addresses. Upon the address matching signal being output, the changing circuit changes write data of the matched addresses to same data.